As the scale down of CMOS technology continues and the demand for portable electronic products driven by batteries increases, many restricting conditions are generated in the design of very large scale integration (VLSI) devices. Typical restricting conditions are demands for low-voltage operation and low power consumption.
As the trend to use of a system on chip (SOC) device is accelerating, not only digital circuits but also analog circuits are integrated in a single chip. Thus, the analog circuits that are typically less affected by the restricting conditions, as compared to the digital circuits, are now equally affected by the restricting conditions.
A circuit that is most widely used among the analog circuits that can be integrated in a single chip may be an operational amplifier. More specifically, a fully differential class AB amplifier having advantages such as noise immunity, wide output swing, and push-pull operation is widely used.
In general, it is difficult to embody a two-stage amplifier with a high gain, for example, a gain over 80 dB. In order to embody a two-stage amplifier having a high gain, a cascode or folded cascade amplifier or a multi-stage amplifier is used.
Although the folded cascade amplifier is able to provide a high gain, however, it is not appropriate for an application having a low operation voltage due to a voltage headroom. Also, the folded cascade amplifier has a complicated bias circuit so that a circuit area increases.
Since the high-gain amplifier is embodied as a multi-stage device, an increase in the circuit area is unavoidable so that a frequency compensation is difficult. Accordingly, due to the necessity for the frequency compensation using a technology such as a nested miller compensation (NMC) or a multi-path NMC (MNMC), problems such as difficult design and power consumption according to the stage increase are present.